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| NTHS4166N Power MOSFET 30 V, 8.2 A, Single N-Channel, ChipFETt Package Features * * * * * Trench Technology Low RDS(on) to Minimize Conduction Losses Leadless ChipFET Package has 40% Smaller Footprint than TSOP-6 Excellent Thermal Capabilities This is a Pb-Free Device http://onsemi.com V(BR)DSS 30 V RDS(on) Max 22 mW @ 10 V ID Max 8.2 A Applications 27 mW @ 4.5 V * Load Switching * DC-DC Converters * Low Side Switching MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Parameter Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current RqJA (Note 1) Power Dissipation RqJA (Note 1) Continuous Drain Current RqJA (Note 2) Power Dissipation RqJA (Note 2) Continuous Drain Current RqJA, t v 5 s (Note 1) Power Dissipation RqJA (Note 1) Pulsed Drain Current TA = 25C TA = 85C TA = 25C Steady State TA = 25C TA = 85C TA = 25C TA = 25C Steady State TA = 85C TA = 25C PD IDM TJ, TSTG IS EAS PD ID PD ID Symbol VDSS VGS ID Value 30 20 6.6 4.8 1.5 4.9 3.6 0.8 8.2 5.9 2.2 32 -55 to 150 2.6 20 W A W A W A 1 ChipFET CASE 1206A STYLE 1 8 Unit V V A G D S N-Channel MOSFET MARKING DIAGRAM AND PIN ASSIGNMENT DDDS 466 M G 1 DDDG 466 = Specific Device Code M = Month Code G = Pb-Free Package TA = 25C, tp = 10 ms ORDERING INFORMATION C A mJ Device NTHS4166NT1G Package ChipFET (Pb-Free) Shipping 3000/Tape & Reel Operating Junction and Storage Temperature Source Current (Body Diode) RqJF Single Pulse Drain-to-Source Avalanche Energy TJ = 25C, VDD = 50 V, VGS = 10 V, IL = 20 Apk, L = 0.1 mH, RG = 25 W Lead Temperature for Soldering Purposes (1/8" from case for 10 s) TL 260 C For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface Mounted on FR4 Board using 1 in sq. pad, 1 oz Cu. 2. Surface Mounted on FR4 Board using the minimum recommended pad size. (c) Semiconductor Components Industries, LLC, 2007 1 December, 2007 - Rev. 0 Publication Order Number: NTHS4166N/D NTHS4166N THERMAL RESISTANCE RATINGS Parameter Junction-to-Ambient - Steady State (Note 3) Junction-to-Ambient - t 5 s (Note 3) Junction-to-Ambient - t 5 s (Note 4) Junction-to-Foot (Drain) Steady State (Note 3) Symbol RqJA RqJA RqJA RqJF Max 86 57 155 20 Unit C/W 3. Surface Mounted on FR4 Board using 1 in sq. pad, 1 oz Cu. 4. Surface Mounted on FR4 Board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Parameter OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage Drain-to-Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(BR)DSS V(BR)DSS/TJ IDSS VGS = 0 V, VDS = 30 V TJ = 25C TJ = 125C Gate-to-Source Leakage Current ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain-to-Source On-Resistance VGS(TH) VGS(TH)/TJ RDS(on) VGS = 10 V, ID = 4.9 A VGS = 4.5 V, ID = 3.7 A Forward Transconductance CHARGES AND CAPACITANCES Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate-to-Source Charge Gate-to-Drain Charge Total Gate Charge Gate Resistance SWITCHING CHARACTERISTICS (Note 6) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time td(on) tr td(off) tf td(on) tr td(off) tf VGS = 10 V, VDS = 15 V, ID = 4.9 A, RG = 3.0 W VGS = 4.5 V, VDS = 15 V, ID = 4.9 A, RG = 3.0 W 12 13 16 5.0 8.0 11 20 4.0 ns ns CISS COSS CRSS QG(TOT) QG(TH) QGS QGD QG(TOT) RG VGS = 10 V, VDS = 15 V, ID = 4.9 A VGS = 4.5 V, VDS = 15 V, ID = 4.9 A VGS = 0 V, f = 1.0 MHz, VDS = 15 V 900 210 140 9.2 0.85 2.86 3.84 18 1.6 nC nC pF gFS VDS = 5 V, ID = 4.9 A VGS = VDS, ID = 250 mA 1.1 5.5 18 23 9.0 22 27 S 2.3 V mV/C mW IGSS VDS = 0 V, VGS = 20 V VGS = 0 V, ID = 250 mA 30 18.3 1.0 10 100 nA V mV/C mA Symbol Test Conditions Min Typ Max Units 5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTHS4166N ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Parameter Symbol Test Conditions Min Typ Max Units DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD VGS = 0 V, IS = 5.2 A TJ = 25C TJ = 125C Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge tRR ta tb QRR VGS = 0 V, IS = 5.2 A, dIS/dt = 100 A/ms 0.83 0.7 16 7.5 8.5 6.0 nC ns 1.0 V 5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 NTHS4166N TYPICAL PERFORMANCE CURVES 15 10 V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 4.5 V 3.6 V 3.4 V 10 TJ = 25C 3.2 V 20 25 VDS 10 V 15 3.0 V 5 2.8 V 10 TJ = 125C 5 TJ = 25C TJ = -55C 1 2 3 4 0 0 0.5 1 1.5 2 2.5 3 0 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 1. On-Region Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) Figure 2. Transfer Characteristics 0.095 0.085 0.075 0.065 0.055 0.045 0.035 0.025 0.015 0.005 2 4 6 8 10 ID = 4.9 A TJ = 25C 0.030 0.028 0.025 0.023 0.020 0.018 0.015 0.013 0.010 5 6 7 8 9 10 11 12 13 14 VGS = 10 V VGS = 4.5 V TJ = 25C VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance vs. Gate-to-Source Voltage RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.6 ID = 4.9 A VGS = 10 V IDSS, LEAKAGE (nA) 1000 10000 Figure 4. On-Resistance vs. Drain Current and Gate Voltage VGS = 0 V 1.4 TJ = 150C 1.2 1.0 100 TJ = 125C 0.8 10 -25 0 25 50 75 100 125 150 5 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.6 -50 Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current vs. Drain Voltage http://onsemi.com 4 NTHS4166N TYPICAL PERFORMANCE CURVES 1400 VGS = 0 V 1200 C, CAPACITANCE (pF) Ciss 1000 800 600 400 200 Crss 0 0 5 10 15 20 25 30 Coss TJ = 25C 10 VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) 8 VGS QT Q2 6 4 Q1 2 ID = 4.9 A TJ = 25C 0 0 2 4 6 8 10 12 14 16 18 DRAIN-TO-SOURCE VOLTAGE (VOLTS) QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate-To-Source and Drain-To-Source Voltage vs. Total Charge 5 IS, SOURCE CURRENT (AMPS) 1000 VDD = 15 V ID = 4.9 A VGS = 10 V t, TIME (ns) 100 td(off) tf tr 10 td(on) VGS = 0 V 4 TJ = 25C 3 2 1 1 1 10 RG, GATE RESISTANCE (OHMS) 100 0 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 100 I D, DRAIN CURRENT (AMPS) 20 Figure 10. Diode Forward Voltage vs. Current ID = 20 A 15 10 1 ms 10 ms 1 VGS = 20 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 dc 10 0.1 5 0.01 0.1 100 0 25 50 75 100 125 150 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 NTHS4166N PACKAGE DIMENSIONS ChipFETt CASE 1206A-03 ISSUE H D 8 7 6 5 q L 5 6 3 7 2 8 1 HE 1 2 3 4 E 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. DIM A b c D E e e1 L HE q MIN 1.00 0.25 0.10 2.95 1.55 MILLIMETERS NOM MAX 1.05 1.10 0.30 0.35 0.15 0.20 3.05 3.10 1.65 1.70 0.65 BSC 0.55 BSC 0.28 0.35 0.42 1.80 1.90 2.00 5 NOM MIN 0.039 0.010 0.004 0.116 0.061 INCHES NOM 0.041 0.012 0.006 0.120 0.065 0.025 BSC 0.022 BSC 0.011 0.014 0.071 0.075 5 NOM MAX 0.043 0.014 0.008 0.122 0.067 e1 e b c STYLE 1: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. GATE 5. SOURCE 6. DRAIN 7. DRAIN 8. DRAIN A 0.05 (0.002) 0.017 0.079 SOLDERING FOOTPRINTS* 1 2.032 0.08 1 2.032 0.08 1.727 0.068 2.362 0.093 0.635 0.025 PITCH 2.362 0.093 8X 8X 0.457 0.018 0.66 0.026 2X 2X mm inches 0.457 0.018 0.66 0.026 Basic *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ChipFET is a trademark of Vishay Siliconix Style 1 mm inches ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 6 NTHS4166N/D |
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